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19-2730; Rev 0; 1/03
10Gbps EAM Driver with Integrated Bias Network
General Description
The MAX3940 is designed to drive an electro-absorption modulator (EAM) at data rates up to 10.7Gbps. It incorporates the functions of a biasing circuit and a modulation circuit, with integrated control op amps externally programmed by DC voltages. The integrated bias circuit provides a programmable biasing current up to 50mA. This bias current reflects a bias voltage of up to 1.25V on an external 50 load. The bias and modulation circuits are internally connected on chip, eliminating the need for an external bias inductor. A high-bandwidth, fully differential signal path is internally implemented to minimize jitter accumulation. When a clock signal is available, the integrated data-retiming function can be selected to reject input-signal jitter. The MAX3940 receives differential CML signals (ground referenced) with on-chip line terminations of 50. The output has a 50 resistor for back termination and is able to deliver a modulation current of 40mA P-P to 120mAP-P, with an edge speed of 23ps (typical, 20% to 80%). This modulation current reflects an EAM modulation voltage of 1.0VP-P to 3.0VP-P. The MAX3940 also includes an adjustable pulse-width control circuit to precompensate for asymmetrical EAM characteristics.
Features
o On-Chip Bias Network o 23ps Edge Speed o Programmable Modulation Voltage Up to 3VP-P o Programmable EAM Biasing Voltage Up to 1.25V o Selectable Data-Retiming Latch o Up to 10.7Gbps Operation o Integrated Modulation and Biasing Functions o 50 On-Chip Input and Output Terminations o Pulse-Width Adjustment o Enable and Polarity Controls o ESD Protection
MAX3940
Ordering Information
PART MAX3940E/D TEMP RANGE -40C to +85C PIN-PACKAGE Dice*
*Dice are designed to operate over a -40C to +120C junction temperature (TJ) range, but are tested and guaranteed at TA = +25C only.
Applications
SONET OC-192 and SDH STM-64 Transmission Systems DWDM Systems Long/Short-Reach Optical Transmitters 10Gbps Ethernet
Typical Application Circuit
-5.2V
0.01F DATA+ 0.01F 50 DATA+
PLRT
MODEN
RTEN
GND EAM
MAX3952
10Gbps SERIALIZER
DATA-
50
DATA-
0.01F CLK+ 0.01F CLK50 CLKPWC+ 2k PWC50 CLK+
MAX3940
OUT 50
MODSET + VMODSET -
BIASSET + VBIASSET -
VEE
-5.2V -5.2V 330pF 0.1F
-5.2V
REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE.
________________________________________________________________ Maxim Integrated Products
1
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10Gbps EAM Driver with Integrated Bias Network MAX3940
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VEE ..............................................-6.0V to +0.5V Voltage at MODEN, RTEN, PLRT, MODSET, BIASSET ...........(VEE - 0.5V) to +0.5V Voltage at DATA+, DATA-, CLK+, and CLK-......-1.65V to +0.5V Voltage at OUT .......................................................-4V to +0.5V Voltage at PWC+, PWC- ...................(VEE - 0.5V) to (VEE + 1.7V) Current into or out of OUT................................................80mA Storage Temperature Range ...........................-55C to +150C Operating Junction Temperature Range..........-55C to +150C Processing Temperature (die)......................................+400C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VEE = -5.5V to -4.9V, TA = -40C to +85C. Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, and TA = +25C, unless otherwise noted.)
PARAMETER Power-Supply Voltage Supply Current Power-Supply Noise Rejection SIGNAL INPUT (Note 3) Input Data Rates Single-Ended Input Resistance Single-Ended Input Voltage Differential Input Voltage Differential Input Return Loss EAM BIAS Maximum Bias Current Minimum Bias Current BIASSET Voltage Range Equivalent Bias Resistance Bias-Current-Setting Accuracy Bias-Current Temperature Stability BIASSET Input Resistance BIASSET Bandwidth EAM MODULATION Maximum Modulation Current Minimum Modulation Current MODSET Voltage Range Equivalent Modulation Resistance VMODSET RMODEQV (Note 7) VMODSET = VEE + 1V VMODSET = VEE VEE 11.1 120 127 38 40 VEE + 1 mAP-P mAP-P V 50 driver load, VBIASSET = VEE + 0.55V, Figure 2 VBIASSET RBSEQV (Note 5) VBIASSET = VEE + 0.11V TA = +25C VBIASSET = VEE + 0.36V VBIASSET = VEE + 2.0V (Note 6) VBIASSET < VEE + 0.36V VBIASSET VEE + 0.36V 2.1 8.8 52 -1300 -480 20 5 VBIASSET = VEE + 2V VBIASSET = VEE VEE 36.4 3.9 11.2 58 +1300 +480 ppm/C k MHz mA 50 55 0.3 1 VEE + 2 mA mA V RIN VIS VID RLIN NRZ Input to GND (Note 3) DC-coupled, Figure 1a AC-coupled, Figure 1b DC-coupled (Note 4) AC-coupled (Note 4) (Note 3) 10GHz 10GHz < f 15GHz 42.5 -1 -0.4 0.2 0.2 17 10 10.7 50 58.5 0 +0.4 2.0 1.6 Gbps V VP-P dB SYMBOL VEE IEE PSNR Excluding IBIAS and IMOD (Note 1) Retime disabled Retime enabled CONDITIONS MIN -5.5 122 139 12 TYP MAX -4.9 170 195 UNITS V mA dB
f 10MHz (Note 2), see Figure 4
2
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10Gbps EAM Driver with Integrated Bias Network
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -5.5V to -4.9V, TA = -40C to +85C. Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, and TA = +25C, unless otherwise noted.)
PARAMETER Modulation Set Bandwidth MODSET Input Resistance Modulation-Current Temperature Stability Modulation-Current Setting Error Output Resistance Total Off Current Output Return Loss Output Edge Speed Setup/Hold Time Pulse-Width Adjustment Range Pulse-Width Control Input Range (Single Ended) Pulse-Width Control Input Range (Differential) Output Overshoot Driver Random Jitter Driver Deterministic Jitter CONTROL INPUTS Input High Voltage Input Low Voltage Input Current VIH VIL (Note 10) (Note 10) (Note 10) -80 VEE + 2.0 VEE + 0.8 +80 V V A RJDR DJDR tSU, tHD RLOUT ROUT (Note 6) 50 driver load, TA = +25C OUT to GND BIASSET = VEE, MODEN = VEE, MODSET = VEE, DATA+ = high, DATA- = low IBIAS = 30mA, IMOD = 50mA Figure 3 (Note 6) (Notes 6, 8) For PWC+ and PWC(PWC+) - (PWC-) (Notes 6, 8) (Note 6) PWC- = GND (Notes 6, 9) 5GHz 8 23 25 20 VEE + 0.5 -0.5 -10 0.3 6.8 50 VEE + 1.5 +0.5 +10 1.1 14 32 -480 -5 42.5 50 SYMBOL CONDITIONS Modulation depth 10%, 50 driver load, see Figure 2 MIN TYP 5 20 +480 +5 58.5 1 MAX UNITS MHz k ppm/C % mA dB ps ps ps V V % psRMS psP-P
MAX3940
20% to 80% (Notes 6, 8)
Note 1: Supply current remains elevated once the retiming function has been enabled. Power must be cycled to reduce supply current after the retiming function has been disabled. Note 2: Power-supply noise rejection is specified as PSNR = 20Log(Vnoise (on Vcc) / VOUT). VOUT is the voltage across a 50 load. Vnoise (on Vcc) = 100mVP-P. Note 3: For DATA+, DATA-, CLK+, and CLK-. Note 4: CLK input characterized at 10.7Gbps Note 5: RBSEQV = (VBIASSET - VEE) / IOUT with MODEN = VEE, DATA+ = high, and DATA- = low. Note 6: Guaranteed by design and characterization using the circuit shown in Figure 4. Note 7: RMODEQV = (VMODSET - VEE) / (IOUT - 37mA) with BIASSET = VEE. Note 8: 50 load, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern. Note 9: Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter). Measured with a 10.7Gbps 27 - 1 PRBS pattern with eighty 0s and eighty 1s inserted in the data pattern. Note 10: For MODEN and PLRT.
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10Gbps EAM Driver with Integrated Bias Network MAX3940
Test Circuits and Timing Diagrams
0V
100mV
1.0V -0.5V
-1.0V (a) DC-COUPLED SINGLE-ENDED CML INPUT
0.4V
800mV 0V 100mV
-0.4V
(b) AC-COUPLED SINGLE-ENDED (CML OR PECL) INPUT
Figure 1. Definition of Single-Ended Input Voltage Range
0V
0V
VOUT
VOUT
VBIASSET (a) MODULATING BIASSET 0V
(c) RESULT OF MODULATING BIASSET AND MODSET 180 OUT OF PHASE
VOUT
mW
POUT
VMODSET (b) MODULATING MODSET NOTE: ALL AMPLITUDES ARE RELATIVE
(d) RESULTING OPTICAL OUTPUT
Figure 2. Modulating BIASSET and MODSET pads
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10Gbps EAM Driver with Integrated Bias Network
Test Circuits and Timing Diagrams (continued)
CLK+ CLKDATADATA+ VIS = 0.1VP-P TO 1VP-P DC-COUPLED 0.1VP-P TO 0.8VP-P AC-COUPLED VIS
MAX3940
tSU
tHD
(DATA+) (DATA-)
VID = 0.2VP-P TO 2VP-P DC-COUPLED 0.2VP-P TO 1.6VP-P AC-COUPLED
IOUT IMOD = 40mAP-P TO 120mAP-P IBIAS = 0mA TO 50mA NOTE: IOUT RELATES TO RETIMED DATA
Figure 3. Setup and Hold Timing Definition
GND
50
50
ROUT 50 OUT 50
OSCILLOSCOPE
50 50 PATTERN GENERATOR 50 DATA+
50 50 ZL
DATA-
IMOD
IBIAS
MAX3940
VEE VEE
VEE -5.2V 0.1F 300pF
MODSET
BIASSET
VEE
VEE
Figure 4. AC Characterization Circuit _______________________________________________________________________________________ 5
10Gbps EAM Driver with Integrated Bias Network MAX3940
Test Circuits and Timing Diagrams (continued)
VOLTAGE GND VBIAS
VMOD
VOUT USABLE RANGE VEE + 1.67V BELOW USABLE RANGE
Figure 5. Bias and Modulation Relationship to EAM Voltage
Typical Operating Characteristics
(Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, TA = +25C, unless otherwise noted.)
10Gbps ELECTRICAL EYE DIAGRAM (VMOD = 1VP-P, 231 - 1 PRBS)
MAX3940 toc01
10Gbps ELECTRICAL EYE DIAGRAM (VMOD = 3VP-P, 231 - 1 PRBS)
MAX3940 toc02
10.3Gbps OPTICAL EYE DIAGRAM
MAX3940 toc03
ASIP, INC. 20ps/div 20ps/div 20ps/div
SUPPLY CURRENT vs. TEMPERATURE (50 LOAD, EXCLUDES IBIAS, IMOD)
MAX3940 toc04
PULSE WIDTH vs. RPWC
RPWC- () 2000 1750 1500 1250 1000 750 500 250 850 PULSE-WIDTH POSITIVE PULSE (ps) 840 830 820 810 800 790 780 770 760 750 MEASURED AT 1.25Gbps WITH A 1010 PATTERN 0
MAX3940 toc05
170 160 150 RETIMING ENABLED IEE (mA) 140 130 120 RETIMING DISABLED 110 100
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
0
250 500 750 1000 1250 1500 1750 2000 RPWC+ ()
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10Gbps EAM Driver with Integrated Bias Network
Typical Operating Characteristics (continued)
(Typical values are at VEE = -5.2V, IBIAS = 30mA, IMOD = 100mA, TA = +25C, unless otherwise noted.)
PULSE-WIDTH DISTORTION vs. TEMPERATURE
MAX3940 toc06
MAX3940
VMOD vs. VMODSET (ZL = 50)
VMODSET IS RELATIVE TO VEE 3.0 2.5 VMOD (VP-P) 2.0 1.5 1.0 0.5 0
MAX3940 toc07
5.0 4.5 PULSE-WIDTH DISTORTION (ps) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
3.5
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
0
0.25
0.50 VMODSET (V)
0.75
1.00
VBIAS vs. VBIASSET (ZL = 50)
MAX3940 toc08
POWER-SUPPLY NOISE REJECTION vs. FREQUENCY
MAX3940 toc09
0 VBIASSET IS RELATIVE TO VEE -0.2 -0.4
30 25 20 PSNR (dB) 15 10 5 0
VBIAS (V)
-0.6 -0.8 -1.0 -1.2 -1.4 -1.6 0 0.5 1.0 1.5 2.0 2.5 VBIASSET (V)
0.1
1
10
100
1000
10,000
FREQUENCY (kHz)
DIFFERENTIAL S11 vs. FREQUENCY
MAX3940 toc10
S22 vs. FREQUENCY (DEVICE POWERED)
-5 -10 |S22| (dB) -15 -20 -25 -30 -35 -40
MAX3940 toc11
0 -5 -10 -15 S11 (dB) -20 -25 -30 -35 -40 -45 -50 -55 -60 0 2 4 6 8
0
10 12 14 16 18 20
0
2
4
6
8
10
FREQUENCY (GHz)
FREQUENCY (GHz)
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10Gbps EAM Driver with Integrated Bias Network MAX3940
Pad Description
PAD BP1, BP2, BP4, BP5, BP7-BP12, BP14, BP15, BP17-BP24, BP26, BP27, BP28 BP3 BP6 BP13 BP16 BP25 BP29 BP30 BP31 BP32 BP33-BP41 BP42 BP43 BP44 NAME FUNCTION
GND
Ground. All pads must be connected to board ground.
DATA+ DATACLK+ CLKOUT MODEN RTEN BIASSET MODSET VEE PWC+ PWCPLRT
Noninverting Data Input, with 50 On-Chip Termination Inverting Data Input, with 50 On-Chip Termination Noninverting Clock Input for Data Retiming, with 50 On-Chip Termination Inverting Clock Input for Data Retiming, with 50 On-Chip Termination Driver Output. Provides both modulation and bias output. DC-couple to EAM. TTL/CMOS Modulation Enable Input. Set low or float for normal operation. Set high to put the EAM in the absorption (logic 0) state. Contains an internal 100k pulldown to VEE. Data-Retiming Input. Connect to VEE for retimed data. Connect to GND to bypass retiming latch. Bias Current Set. Apply a voltage to set the bias current of the driver output. Modulation Current Set. Apply a voltage to set the modulation current of the driver output. Negative Supply Voltage. All pads must be connected to VEE. Positive Input for Modulation Pulse-Width Adjustment (see the Design Procedure section). Negative Input for Modulation Pulse-Width Adjustment. Ground to disable the pulse-width adjustment feature (see the Design Procedure section). Differential Data Polarity Swap Input. Set high or float for normal operation. Set low to invert the differential signal polarity. Contains an internal 100k pullup to GND.
Detailed Description
The MAX3940 EAM driver consists of two main parts: a high-speed modulation driver and an EAM-biasing block. The clock and data inputs to the driver are compatible with PECL and CML logic levels. The modulation and bias current are output through the OUT pad. The modulation output stage is composed of a highspeed differential pair and a programmable current source with a maximum modulation current of 120mA. The rise and fall times are typically 23ps. The modulation current is designed to produce an EAM voltage up to 3.0VP-P when driving a 50 module. The 3.0VP-P results from 120mAP-P through the parallel combination of the 50 EAM load and the internal 50 back termination.
Polarity Switch
The MAX3940 includes a polarity switch. When the PLRT pad is high or left floating, the output maintains the polarity of the input data. When the PLRT pad is low, the output is inverted relative to the input data.
Clock/Data Input Logic Levels
The MAX3940 is directly compatible with ground-reference CML. Either DC- or AC-coupling may be used for CML referenced to ground. For all other logic types, AC-coupling should be used.
Optional Data Input Latch
To reject pattern-dependent jitter in the input data, a synchronous differential clock signal should be connected to the CLK+ and CLK- inputs, and the RTEN control input should be connected to VEE.
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10Gbps EAM Driver with Integrated Bias Network
The input data is retimed on the rising edge of CLK+. If RTEN is connected to ground, the retiming function is disabled and the input data is directly connected to the output stage. Leave CLK+ and CLK- open when retiming is disabled.
MAX3940
VBIAS IBIAS x
ZL x ROUT ZL + ROUT
Pulse-Width Control
The pulse-width control circuit can be used to compensate for pulse-width distortion introduced by the EAM. The differential voltage between PWC+ and PWCadjusts the pulse-width compensation. The adjustment range is typically 50ps. Optional single-ended operation is possible by forcing a voltage on the PWC+ pad while leaving the PWC- pad unconnected. When PWCis connected to ground, the pulse-width control circuit is automatically disabled.
To program the desired bias current, force a voltage at the BIASSET pad (see the Typical Application Circuit). The resulting IBIAS current can be calculated by the following equation: IBIAS VBIASSET 36.4
The input impedance of the BIASSET pad is typically 20k. Note that the minimum output voltage is VEE + 1.67V (see Figure 5).
Programming the Pulse-Width Control
Three methods of control are possible when pulse predistortion is desired to minimize distortion at the receiver. The pulse width may be set with a 2k potentiometer with the center tapped to VEE (or equivalent fixed resistors), or by applying a voltage to the PWC+ pad, or by applying a differential voltage across the PWC+ and PWC- pads. See Table 1 for the desired effect of the pulse-width setting. Pulse width is defined as (positive pulse width)/((positive pulse width + negative pulse width)/2).
Modulation Output Enable
The MAX3940 incorporates a modulation currentenable input. When MODEN is low or floating, the modulation/bias output (OUT) is enabled. When MODEN is high, the output is switched to the logic 0 state. The typical enable time is 2ns and the typical disable time is 2ns.
Design Procedure
Programming the Modulation Voltage
The EAM modulation voltage results from IMOD passing through the EAM impedance (ZL) in parallel with the internal 50 termination resistor (ROUT). VMOD IMOD x ZL x ROUT ZL + ROUT
Input Termination Requirement
The MAX3940 data and clock inputs are CML compatible. However, it is not necessary to drive the IC with a standard CML signal. As long as the specified input voltage swings are met, the MAX3940 will operate properly.
Applications Information
Layout Considerations
To minimize loss and crosstalk, keep the connections between the MAX3940 output and the EAM module as short as possible. Use good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Circuit boards should be made using low-loss dielectrics. Use controlled-impedance lines for the clock and data inputs as well as for the data output. Wafer capacitors are required to filter the VEE supply. Connect the backside of the die to GND.
To program the desired modulation current, force a voltage at the MODSET pad (see the Typical Application Circuit). The resulting IMOD current can be calculated by the following equation: IMOD VMODSET + 37mA 11.1
An internal, independent current source drives a constant 37mA to the modulation circuitry and any voltage above VEE on the MODSET pad adds to this. The input impedance of the MODSET pad is typically 20k. Note that the minimum output voltage is VEE + 1.67V (see Figure 5).
Table 1. Pulse-Width Control
PULSE WIDTH 100% >100% <100% RPWC+, RPWC- FOR RPWC+ + RPWC- = 2k RPWC+ = RPWCRPWC+ > RPWCRPWC+ < RPWCVPWC+ (PWC- OPEN) VEE + 1V > VEE + 1V < VEE + 1V VPWC+ VPWC0V >0V <0V
Programming the Bias Voltage
As in the case of modulation, the EAM bias voltage results from IBIAS passing through the EAM impedance (ZL) in parallel with the internal 50 termination resistor (ROUT).
_______________________________________________________________________________________
9
10Gbps EAM Driver with Integrated Bias Network MAX3940
RTEN MODEN PLRT
50 50 50 50 50 ROUT 50 OUT VEE ZL
CLK+ CLK-
D
Q
0 MUX PWC
POLARITY
DATA+ 1 DATA50 50 IMOD IBIAS
MAX3940
VEE VEE
PWC+
PWC-
MODSET + VMODSET VEE +
BIASSET VBIASSET VEE
2k
VEE
Figure 6. Functional Diagram
Interface Schematics
Figures 7 and 8 show simplified input and output circuits of the MAX3940 EAM driver.
Laser Safety and IEC 825
Using the MAX3940 EAM driver alone does not ensure that a transmitter design is compliant with IEC 825. The entire transmitter circuit and component selections must be considered. Each customer must determine the level of fault tolerance required by their application, recognizing that Maxim products are not designed or authorized for use as components in systems intended for surgical implant into the body, for applications intended to support or sustain life, or for any other application where the failure of a Maxim product could create a situation where personal injury or death may occur.
Wire Bonding Die
For high-current density and reliable operation, the MAX3940 uses gold metalization. Make connections to the die with gold wire only, using ball-bonding techniques. Minimize bond-wire lengths and ensure that the span between the ends of the bond wire does not come closer to the edge of the die than two times the bond-wire diameter. The minimum length of the bond wires might be constrained by the type of wire bonder used, as well as the dimensions of the die. To minimize inductance, keep the connections from OUT, GND, and VEE as short as possible. This is crucial for optimal performance.
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______________________________________________________________________________________
10Gbps EAM Driver with Integrated Bias Network MAX3940
GND
GND
50 50
GND
MAX3940
MAX3940
50
DATA+/CLK+
50
GND OUT VEE
50 GND
DATA-/CLK-
VEE
Figure 7. Simplified Input Circuit
Figure 8. Simplified Output Circuit
Chip Topography/ Pad Configuration
The origin for pad coordinates is defined as the bottom left corner of the bottom left pad. All pad locations are referenced from the origin and indicate the center of the pad where the bond wire should be connected. Refer to Maxim application note HFAN-08.0.1: Understanding Bonding Coordinates and Physical Die Size for detailed information. Maxim characterized this circuit with gold wire (1-mil diameter wire) ball bonded to the pads. Die pad size is 4 mils (102m) square, and die thickness is 8 mils (203m).
Chip Information
TRANSISTOR COUNT: 2084 PROCESS: SiGe BIPOLAR SUBSTRATE: SOI DIE THICKNESS: 8 mils
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11
10Gbps EAM Driver with Integrated Bias Network MAX3940
Chip Topography
PLRT PWCPWC+ VEE VEE VEE VEE VEE VEE VEE VEE VEE MODSET BIASSET RTEN MODEN
GND GND GND GND DATA+ GND
GND GND DATA-
OUT
1.6mm (63 mils)
GND GND GND GND GND
(0, 0) GND GND GND GND CLK+ GND GND 2.3mm (90.6 mils) CLKGND GND GND GND GND
12
______________________________________________________________________________________
10Gbps EAM Driver with Integrated Bias Network MAX3940
Table 2. Bondpad Locations
PAD NUMBER BP1 BP2 BP3 BP4 BP5 BP6 BP7 BP8 BP9 BP10 BP11 BP12 BP13 BP14 BP15 BP16 BP17 BP18 BP19 BP20 BP21 BP22 PAD NAME GND GND DATA+ GND GND DATAGND GND GND GND GND GND CLK+ GND GND CLKGND GND GND GND GND GND COORDINATES (m) X 51.2 51.2 51.2 51.2 51.2 51.2 51.2 51.2 231.8 357.8 483.8 609.8 769.4 895.4 1021.4 1147.4 1305.2 1431.2 1606.2 1732.2 1874 2028 Y 933.2 807.2 681.2 555.2 429.2 303.2 177.2 51.2 -63.6 -63.6 -63.6 -63.6 -63.6 -63.6 -63.6 -63.6 -63.6 -63.6 -63.6 -63.6 -63.2 -43.8 PAD NUMBER BP23 BP24 BP25 BP26 BP27 BP28 BP29 BP30 BP31 BP32 BP33 BP34 BP35 BP36 BP37 BP38 BP39 BP40 BP41 BP42 BP43 BP44 PAD NAME GND GND OUT GND GND GND MODEN RTEN BIASSET MODSET VEE VEE VEE VEE VEE VEE VEE VEE VEE PWC+ PWCPLRT COORDINATES (m) X 2028 2028 2028 2028 2028 2028 1953.8 1827.8 1701.8 1575.8 1449.8 1323.8 1197.8 1071.8 945.8 819.8 693.8 567.8 441.8 315.8 189.8 63.8 Y 108.6 234.6 574.8 700.8 856.2 982.2 1140.4 1140.4 1140.4 1140.4 1140.4 1140.4 1140.4 1140.4 1140.4 1140.4 1140.4 1140.4 1140.4 1140.4 1140.4 1140.4
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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